Semiconductor memory manufacturing technology allows the creation of high density memories on an integrated circuit chip. Such memories typically consist of an array of many memory cells arranged in a matrix of rows and columns. Each memory cell can be uniquely addressed by its particular row and column. The cell array is sometimes divided into numerous subarrays that share certain peripheral and interface components such as, for example, shared sense amplifiers, column select lines, and input/output (I/O) lines for performing reading and writing operations.
Sharing components and control signals, such as between the subarrays, allows efficient utilization of available integrated circuit chip area and may reduce power consumption. However, shared components and signals may constrain data accessibility. In a memory in which components and signals are shared, each memory cell is still uniquely addressable. However, not all memory cells are simultaneously addressable due to the shared components. As a result, the throughput of the reading and writing operations is reduced. There is a need in the art to provide a memory architecture that allows the sharing of components and signals and also provides more flexible addressing of memory cells to enhance the speed of reading and writing operations and to provide more robust timing during these operations.